There is currently a great interest in the provision of small device structures, largely as a result of the increasing requirements for higher packing density for VSLI integrated circuits. As the dimensions of the structure of the device shrinks in order to achieve high packing density, the sheet resistance associated with the gate increases. This increased sheet resistance contributes to RC propagation delays.
Polysilicon has been the dominant interconnect material since it has a low threshold voltage and also provides good step coverage with uniform and economical deposition of the layers. Its high temperature characteristics aid in stability during annealing, after the etching and ion implantation steps. Due to the problem of high sheet resistance of the material, however, various methods have been tried to find other interconnect materials with lower resistance.
One of the primary considerations is obtaining a material with high electrical conductivity and low ohmic contact resistance. The material should also have electromigration resistance and be stable in final metallization in contact with silicon and/or oxide. These characteristics must be maintained throughout the high temperature processing.
Presently, a polycide structure composed of polysilicon and a transition metal silicide appears to meet these requirements. Because of its relatively high conductivity, polycide has been selected as a material for VSLI devices.
Since the channel length of the device shrinks continuously toward the submicron region, however, the sheet resistance of polycide cannot be reduced to meet higher performance requirements.
A gate interconnect of pure refractory metal still seems attractive since refractory metal has the important advantage of very low resistivity compared with polysilicon and silicides. It cannot, however, withstand high temperature oxidation to which it is exposed during processing. In addition, some chemical reagents utilized to clean the wafers during processing cannot be tolerated by most refractory metals.
U.S. Pat. No. 4,755,478, Abernathy et al, discloses a method for making a planarized gate stack having a low sheet resistance, the method including disposing a gate mask on the top of a patterned polysilicon layer. Subsequently the insulating layer is planarized to expose the upper surface of the gate mask, which is then etched to expose the polysilicon layer, and a conductive material, primarily a refractory metal, is grown to provide a metal strapped polysilicon gate electrode.
U.S. Pat. No. 4,514,233, Kawabuchi, discloses a method for reducing the resistance of the gate electrode including the steps of forming a silicon nitride film, doping the source and drain regions using tee silicon nitride as a mask, and removing the silicon nitride to expose the gate electrode for final aluminum wiring connections.
U.S. Pat. No. 4,616,401, Takeuchi, discloses a method wherein conductive material films are formed on the gate electrode as well as on the source and drain regions.
U.S. Pat. No. 4,676,867, Elkins et al, discloses a method for applying a first layer of a dielectric material over a metal layer using a layer of spin-on-glass for planarization, and applying a second layer of dielectric over the first dielectric layer before defining the electrode paths.
U.S. Pat. No. 4,753,709, Welch et al, discloses a method for etching contact paths of different depth utilizing a silicide film which acts as an etch stop, without etching through any of the polysilicon layers.
U.S. Pat. No. 4,780,429, Roche et al, discloses a method for forming a gate electrode by a first layer of metallic silicide followed by a second layer of metallic silicide to be used as source and drain electrodes, without forming a composite gate electrode.